Many integrated circuit memory devices include sense amplifiers to facilitate writing and reading of data to and from an array of memory devices therein. As will be understood by those skilled in the art, sense amplifiers typically perform a function of sensing a relatively small differential input signal across a pair of differential input lines and then amplifying the small differential input signal by driving a pair of differential output lines rail-to-rail (e.g., Vdd-to-GND) with a differential output signal. An exemplary sense amplifier is disclosed in U.S. Pat. No. 5,701,268 to Lee et al., entitled "Sense Amplifier for Integrated Circuit Memory Devices Having Boosted Sense and Current Drive Capability and Methods of Operating Same", assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
Referring now to FIG. 1, an electrical schematic of an integrated circuit memory device according to the prior art will be described. In this prior art memory device, a plurality of separate memory cell arrays 101 and 102 can be electrically coupled one-at-a-time to a single sense amplifier 111. Access to the first memory cell array 101 is provided by a first plurality of pairs of differential input/output lines. This first plurality of pairs of differential input/output lines may be a first plurality of pairs of complementary bit lines (BL1, BLB1, . . . , Bln, BLBn, where n is an odd integer). As illustrated, a first pair of complementary bit lines BL1 and BLB1 may be used to write data to or read data from a plurality of memory cells in the first memory cell array 101. A first equalization circuit 121 and a first isolation gate 131 are electrically coupled between the first memory cell array 101 and the sense amplifier 111. A first equalization circuit controller 141 and first isolation gate controller 151 are also provided. The first isolation gate 131 is responsive to a logic 1 signal on a first isolation signal line PISOi, and the first equalization circuit 121 and the first equalization circuit controller 141 are responsive to signals on a pair of first equalization signal lines PEQi and PEQiB.
As illustrated, the first equalization circuit 121 comprises a plurality of NMOS transistors and the first equalization circuit controller 141 is configured as an NMOS pull-down transistor. Based on this configuration, if the first equalization signal line PEQi is set to a logic 1 potential, the complementary first equalization signal line PEQiB will be pulled to a logic 0 potential to turn-off the NMOS transistors in the first equalization circuit 121. However, if the first equalization signal line PEQi is set to a logic 0 potential, the complementary first equalization signal line PEQiB may be held at a logic 1 potential so that the NMOS transistors in the first equalization circuit may be turned-on to thereby electrically short the complementary bit lines together. In this latter case, the first pair of complementary bit lines BL1 and BLB1 may be set to an equalized and precharged potential of 1/2Vdd, prior to or after a reading or writing operation is performed. As will be understood by those skilled in the art, after the first pair of complementary bit lines BL1 and BLB1 have been set to an equalized precharged potential (e.g., 1/2Vdd), a reading or writing operation may be performed by driving both the first equalization signal line PEQi and the first isolation signal line PISOi to a logic 1 potential so that the first pair of complementary bit lines BL1 and BLB1 become electrically connected via the first isolation gate 131 to a first pair of input/output lines at the sense amplifier 111. Driving the first equalization signal line PEQi to a logic 1 potential will turn on the NMOS pull-down transistor in the first equalization circuit controller 141 and pull-down the complementary first equalization signal line PEQiB so that the first equalization circuit 121 is turned off.
Similarly, access to the second memory cell array 102 is provided by a second plurality of pairs of differential input/output lines. This second plurality of pairs of differential input/output lines may be a second plurality of pairs of complementary bit lines (BL2, BLB2, . . . , Bln+1, BLBn+1, where n is an odd integer). As illustrated, a second pair of complementary bit lines BL2 and BLB2 may be used to write data to or read data from the second memory cell array 102. A second equalization circuit 122 and a second isolation gate 132 are electrically coupled between the second memory cell array 102 and the sense amplifier 111. A second equalization circuit controller 142 and a second isolation gate controller 152 are also provided. The second isolation gate 132 is responsive to a logic 1 signal on a second isolation signal line PISOj and the second equalization circuit 122 and second equalization circuit controller 142 are responsive to signals on a pair of second equalization signal lines PEQj and PEQjB.
The second equalization circuit 122 comprises a plurality of NMOS transistors and the second equalization circuit controller 142 is configured as an NMOS pull-down transistor. Based on this configuration, if the second equalization signal line PEQj is set to a logic 1 potential, the complementary second equalization signal line PEQjB will be pulled to a logic 0 potential to turn-off the NMOS transistors in the second equalization circuit 122. However, if the second equalization signal line PEQJ is set to a logic 0 potential, the complementary second equalization signal line PEQjB may be held at a logic 1 potential so that the NMOS transistors in the second equalization circuit may be turned-on. In this latter case, the second pair of complementary bit lines BL2 and BLB2 may be set to an equalized and precharged potential of 1/2Vdd, prior to or after a reading or writing operation. As will be understood by those skilled in the art, after the second pair of complementary bit lines BL2 and BLB2 have been set to an equalized precharged potential (e.g., 1/2Vdd), a reading or writing operation may be performed by driving both the second equalization signal line PEQj and the second isolation signal line PISOj to a logic 1 potential so that the second pair of complementary bit lines BL2 and BLB2 become electrically connected via the second isolation gate 132 to a second pair of input/output lines at the sense amplifier 111.
Unfortunately, the cross-coupled electrical connections between the first isolation gate controller 151 and the second equalization circuit controller 142 and between the second isolation gate controller 152 and the first equalization circuit controller 141 preclude the simultaneous formation of electrical connections between the sense amplifier 111 and the first and second memory cell arrays 101 and 102. For example, if the sense amplifier 111 is electrically coupled to the first memory cell array 101 by driving the first equalization signal line PEQi and the first isolation signal line PISOi to logic 1 potentials, then the second isolation signal line PISOj will be pull-down to a logic 0 potential by operation of the second isolation gate controller 152 which has its control input (e.g., gate electrode) electrically connected to the first equalization signal line PEQi. Alternatively, if the sense amplifier 111 is electrically coupled to the second memory cell array 102 by driving the second equalization signal line PEQj and the second isolation signal line PISOj to logic 1 potentials, then the first isolation signal line PISOi will be pull-down to a logic 0 potential by operation of the first isolation gate controller 151 which has its control input (e.g., gate electrode) electrically connected to the second equalization signal line PEQj. Thus, the prior art memory device of FIG. 1 does not allow the sense amplifier 111 to be simultaneously connected to both the first and second memory cell arrays 101 and 102 to enable simultaneous reading from these arrays when performing burn-in stress testing and other operations.